ORX-10G-123S6 Release Notes
Product Information
Product: ORX-10G-123S6
Firmware Version: 2411.0.120.0
Note: Oryx part numbers with 10G and 10GS are functionally the same and differ only in dimensions and mass. (10GS is the smaller camera.)
Bugs Fixed
| Bug | Description |
|---|---|
| Firm-12533 | Addressed extended line time which resulted in chunk exposure being wrong |
| Firm-9279 | Implemented PHY reset to address camera enumeration |
| Firm-12435 | Failed to enumerate with Spinnaker version 4.0 and later |
| Firm-12528 | Chunk Exposure Time did not match exposure time |
| Firm-5173 | Updated shadow variable when persistent IP was forced. |
| Firm-6730 | FPGA and Firmware lost sync in the Ethernet receive buffer under high packet traffic. |
| Firm-6036 | Reset receive FIFO when error occurs so that the command interface does not lock up. |
| Firm-5071 | Fixed issue that Camera LED was solid green while acquisition not enabled |
| Firm-5204 | Removed clamping from set_frame_time to correct behavior during user set load |
| Firm-5203 | Added fix for 10-bit packed pixel formats to correct max pixel dynamic range value |
| Firm-4203 | Fixed framerate getting stuck at 1 Hz when the framerate is not changed manually |
| Firm-4004 | The frame rate node will be remembered when the user enters it externally. If a node changes that forces the frame rate to a different value, when the node is gain changed and the remembered frame rate is within the valid range then it will return to this value. |
| Firm-3581 | Fixed IP conflict detection when target IP address matches ours for an ARP packet. |
| Firm-3621 | Added SequencerConfigurationReset node. |
| Firm-2054 | CAM ABORT when facing image fifo overflow |
| Firm-2959 | Exposure time offset and other pulsegen registers could only be set after the sensor clock has been enabled. |
| Firm-2515 |
1 Merge in 10-bit
pixel format from trunk. 2 Fixed issue with IMX25X FPGA build with incorrect constraints for M1 DDR. 3 Add expanded image memory to IMX25X. |
| Firm-2516 | Merged exposure offset fix to IMX250/253/255. |
| Firm-1081 | The digital I/O line source can have an "Off" state for output only lines. |
| Firm-497 | Fixed an issue preventing the camera to sync to ptp master. |
| Firm-697 | Camera to acknowledge the device reset command before executing the reset. |
| Firm-520 | Changed Cachable property, for auto algorithm features, from WriteAround to NoCache and added PollingTime of 500. |
| Firm-1532 | Removed duplicate enum entry in GevSupportedOptionSelector |
| Firm-1082 | Added the ability to reserve a little portion of the link bandwidth for gvcp packets when the safe max frame rate was calculated. |
| Firm-910 | Cleared flash extended addressing mode before a cold reboot. Improves reboot time. |
| Firm-611 | Modified default network speed to 10G for Oryx when the network is not available yet. |
| Firm-227 | Switched to latest version of Ethernet PHY firmware along with FPGA that fixes some problems. |
| Firm-101 | Decoupled GVCP requests from replies and moved reply transmission to the interface task. This allows ARP table to be accessed in a thread safe manner. |
| Firm-59 | Updated DocFilter to include the OpenDrain enum entry. |
| Firm-328 | Changed line format of non-opto lines to be read as OpenDrain instead of TTL. |
| Firm-227 |
1 Moved packet
size boundary checking from temec_read to hw_recv. The reason for this is
that hw_recv allocates packet buffer memory and if the FPGA sends us a
spurious packet (which as right now happens quites a bit with the latest PHY
firmware version), we don't want to allocate an abnormal amount (and run out)
or allocate something less than the ethernet header size and later crash.
Leave the max_len boundary checking in temac_read alone. 2 Do NULL pointer checking on the (destination) packet buffer. Also, if NULL is passed (i.e. when a packet buffer cannot be allocated), "consume" the packet without copying it anywhere. This behaviour appears to be expected by hw_send, but was not implemented by temac_read. |
| Firm-126 |
1 When PHY
state changes set speed before resetting TX/RX FPGA components. This seems to
prevent spurious rx packets when switching between 10G to 1G. 2 Don't allocate memory for packets deemed to be spurious (payload length above a standard 1500 byte IP packet + Ethernet header). |
Changes
| Change | Description |
|---|---|
| NA | None |
Known Issues
| Issue | Description |
|---|---|
| NA | None |
